FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6021 Discussions

FIFO Simulation Modelsim Timing Error

Sahil_Honeywell
New Contributor I
178 Views

Hi, 

I am writing a simple test bench for 8-bit FIFO. During simulation in Modelsim, when the 'write_fifo' signal turns high, it becomes red (X). Everything else remains fine. The 'read_fifo' signal is fine. Can you please tell me what I am doing wrong and how can I correct it. Please find snapshots and code in the attachment. 

Am I doing something wrong with 'write_fifo' signal with respect to FIFO 'clock'?

0 Kudos
1 Reply
Sahil_Honeywell
New Contributor I
160 Views

I figured this out. My test bench was wrong. I was triggering write signal instead of read signal in multiple processes. After correction it works fine now.

Reply