I have been trying to make a project using HPS to read some data from ADC. My ADC has I2S interface and I configured it to MSB justified format. Later the received data is sent to FIR II, so I build a streaming interface in my I2S peripheral.
Right now, because I want to see data without the FIR filter so I connect my I2S peripheral to a Avalon FIFO Memory IP in Qsys. The FIFO is in Streaming to Memory Mapped mode. The output of FIFO is connected to an mSGDMA, which will write the data to a buffer in my HPS.
Briefly, the whole design is like this
ADC --> I2S peripheral --> (streaming) FIFO (memory mapped)--> mSGDMA --> HPS
The picture above is my I2S-MSB justified with built-in Streaming interface. My interface keeps the data out = 'Z' and does not pull high the valid signal until 32-bit is completely received.
For example, when the WS signal in on channel 1, then the output of channel 2 is 'Z' and output of channel 1 is also 'Z' until the 32th bit is received. Once the 32 bits are received, my streaming interface will pull high the valid signal and wait until the ready signal is asserted then send out the data. It works the same way when WS signal of I2S is on channel 2.
My question is that: Does my design somehow cause the loss of sampled data? I believe that if the valid signal is not asserted and data is 'Z', then nothing is written into my FIFO. Somehow, when I was reading the data from ADC, I saw some 0 data ( while it is not supposed to be). Especially, when I start my program and I will 0 data for a while, like a delay, before receiving something. Do I miss something with the FIFO IP 😕 ?
If you guys say it is ok with my design, then I will triple-check my ADC.
Thanks in advance and sorry for such a long post 😁. Any suggestion or clue or comment is welcomed.
I couldn't find any related design or documentation that I could refer to help with your case.
May I know which Avalon FIFO Memory IP are you using in the Qsys?