Hi,I'm using a 32 bit FIFO set to show-ahead, to cross clock domains from a fast clock to a slower clock. The FIFO is empty and i clock in two 32 bit words, i invert the rdempty signal and use this as the read request .However after the 2 word have been written to the FIFO the wrusedw indicates that the fifo now has 1023 words of data. I have attached a screen shot of signal tap. The signaltap is clocked from the FIFO Write clock so the width of the signals are wrong but it shows the FIFO filling up. any ideas to why this is happening? http://www.alteraforum.com/forum/attachment.php?attachmentid=11952&stc=1
Did you write your own FIFO logic?It seems that the extra read cycle from the second read causing the FIFO counter to loop (overflow) to maximum value of 1023. If you write your own logic, you might want to detect the counter == 0 and prevent the read.