I'd like to use the FIR Compiler 2 in my Verilog project, but it seems like the output it produces is mostly VHDL with a Verilog wrapper. This would be fine, but I'd like to simulate my design in Modelsim-altera which doesn't work with mixed VHDL/Verilog.
Does anyone know if it's possible to either generate verilog simulation libraries like you could in FIR Compiler 1, or a work around to simulating with the VHDL libraries in an otherwise Verilog project?
