FIR II Coefficient Reload Problems

[Patrik78]

Hello, 

I am using Quartus version 18.1 and I have a FIR filter in a Nios II QSYS system (created with FIR II). the filter works as expected with the preconfigured coefficients in QSYS. 

The issue is when trying to reconfigure the FIR coefficients by MM interface, in this case trying to read one coefficient at first address deadlocks the whole system.

The interface is configured as read/write. 

I've found a few similar problems here in the community but without an Intel official reply:

https://community.intel.com/t5/FPGA-Intellectual-Property/FIR-Coefficient-Reload-Problmes/m-p/239608

https://community.intel.com/t5/FPGA-Intellectual-Property/Altera-FIR-Compiler-II-15-0-Coefficients-Reload-Issues/m-p/67840

https://community.intel.com/t5/FPGA-Intellectual-Property/FIR-II-Coefficient-Read-from-Cyclone-V-HPS-Freezing/m-p/6808480

Is there a way to get an official Intel answer?

[Kshitij_Intel]

Hi,

Are you following the same timing diagram(as mentioned in the link below) as per your mode?

https://www.intel.com/content/www/us/en/docs/programmable/683208/17-1/fir-ii-ip-core-coefficient-reloading.html

Thank you

Kshitij Goel

[Patrik78]

Hi,

actually the system is composed by Platform Designer, and all the read accesses are made by a Nios II processor.

The read access is simply done by a predefined IORD(), as per all the other MM slave in the system that works correctly.

So I expect this IORD follow the correct timing diagram.

Unlucky reading the one coefficient at first address deadlocks the processor that stop works. Otherwise everything works correctly.

Any ideas?

[Kshitij_Intel]

Hi,

You must toggle the coeff_in_areset signal before reloading the coefficient with new data. The new coefficient data is read out after coefficient reloading to verify whether the coefficient reloading process is successful. When the coefficient reloading ends by de-asserting the coeff_in_we, the input data is inserted immediately to the filter that is reloaded with the new coefficients.

Thank you

Kshitij Goel

[Kshitij_Intel]

Hi,

Please process the signals as mentioned in the timing waveform. Share the screenshot for the same. Please refer the link below.

https://www.intel.com/content/www/us/en/docs/programmable/683208/17-1/fir-ii-ip-core-coefficient-reloading.html

If even after following the timing FIR II IP giving issues. Please share your project then.

Thank you

Kshitij Goel

[Kshitij_Intel]

Hi,

As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you

Kshitij Goel