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Altera_Forum
Honored Contributor I
1,326 Views

FIR and CIC MegaCores Altogether

Hi, 

I have instantiated FIR II MegaCore as a Pulse-Shaping and upsampling by 8 filter, now I want to use CIC MegaCore 

after FIR to interpolate the signal... I didn't use Back Pressure feature in FIR. 

Simulation shows that signal is not interpolated... almost the same. In the generated test bench of the CIC IP, I noticed that input is allowed only 

when "in_ready" signal is high... when it's low the input is kept hold. 

I tried to do the same thing using Back Pressure feature in FIR IP, but because ModelSim doesn't allow mixed-HDL simulations 

(what a shame!) I couldn't verify. So, I used SignalTap instead... plotting the result on MATLAB shows a completely 

distorted signal! 

 

So... How do I use CIC along with FIR MegaCore? Can you please provide an example?
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15 Replies
Altera_Forum
Honored Contributor I
46 Views

 

--- Quote Start ---  

Hi, 

I have instantiated FIR II MegaCore as a Pulse-Shaping and upsampling by 8 filter, now I want to use CIC MegaCore 

after FIR to interpolate the signal... I didn't use Back Pressure feature in FIR. 

Simulation shows that signal is not interpolated... almost the same. In the generated test bench of the CIC IP, I noticed that input is allowed only 

when "in_ready" signal is high... when it's low the input is kept hold. 

I tried to do the same thing using Back Pressure feature in FIR IP, but because ModelSim doesn't allow mixed-HDL simulations 

(what a shame!) I couldn't verify. So, I used SignalTap instead... plotting the result on MATLAB shows a completely 

distorted signal! 

 

So... How do I use CIC along with FIR MegaCore? Can you please provide an example? 

--- Quote End ---  

 

 

If you don't have back pressure feature on FIR then I suggest using fifo between FIR and CIC
Altera_Forum
Honored Contributor I
46 Views

I do have it... but I can't simulate it... however, I used SignalTap to observe the output... it was distorted. 

I connected "in_ready" output signal of CIC to the input "ast_source_ready" of FIR. I don't think there is much to do. Or is there?
Altera_Forum
Honored Contributor I
46 Views

 

--- Quote Start ---  

I do have it... but I can't simulate it... however, I used SignalTap to observe the output... it was distorted. 

I connected "in_ready" output signal of CIC to the input "ast_source_ready" of FIR. I don't think there is much to do. Or is there? 

--- Quote End ---  

 

 

when cic is ready for input the fir will then produce ouput late due to FIR latency. 

You need to have CIC input ready when it asks for it. I think a fifo will do. write to fifo FIR output on valid out and read fifo on CIC in_ready with enough fifo depth.
Altera_Forum
Honored Contributor I
46 Views

I changed the CIC clock to 10 MHz, it was 100 MHz... output of FIR is around 1.42 MSPS and interpolation factor is 7. 

And this is my configuration: 

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=10272&stc=1  

 

In SignalTap I got this: 

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=10273&stc=1  

 

You can see that CIC is producing samples like bursts (dout and out_valid signals) 

And it is accepting samples all the time (RRC: ast_source_ready signal) 

RRC is driving its output_ready signal along with CIC's out_valid. (This is strange) 

I used edge detector to drive CIC's in_valid signal. 

 

All that resulted in this: 

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=10274&stc=1  

 

After deleting samples that aren't associated with validity signal... I got this: 

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=10275&stc=1  

 

Which I need to have as a direct output of the CIC. 

I feel that outputs of FIR and CIC should be swapped... I mean FIR must provide data as bursts 

and CIC must spite out samples continuously. 

 

I think there is something to do with what you've just mentioned... don't you think that Back Pressure should handle this? It's enabled!
Altera_Forum
Honored Contributor I
46 Views

Before committing yourself further may I ask why you don'y use RRC for all your interpolation without the need for CIC. 

You will need higher taps but interpolation plus clk ratio will help reduce mults considerably.
Altera_Forum
Honored Contributor I
46 Views

My original data rate is 176.4 KHz, and I want to raise to to 100 MHz so that I can multiply it with the carrier signal. 

that means an interpolation factor of 566!!! Isn't that too much?! I wish I could do it in a single stage but I thought it would be 

a waste of resources. If you recommend it I will do it :) 

 

EDIT: I've just checked the FIR compiler... it doesn't have such a factor. Maximum is 128.
Altera_Forum
Honored Contributor I
46 Views

I solved it KAZ :D 

I did what you suggested... using FIFO... You are GENIUS! 

 

So this is the new configuration: 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=10278  

 

And SignalTap shows exactly what I want: 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=10279  

 

To satisfy ourselves... here is the signal before interpolation (RRC output): 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=10280  

 

And this is after interpolation: 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=10281  

 

Thank you again :)
Altera_Forum
Honored Contributor I
46 Views

Now the question is you are interpolating from 176.4KHz to 100MHz. The ratio is fractional and so you need to do fractional interpolation. 

Alternatively set DAC to multiple of 176.4KHz
Altera_Forum
Honored Contributor I
46 Views

There is also issue of using different clock rates on FIR and CIC. Do you need that. You better use same system clock or it may go wrong

Altera_Forum
Honored Contributor I
46 Views

 

--- Quote Start ---  

Now the question is you are interpolating from 176.4KHz to 100MHz. The ratio is fractional and so you need to do fractional interpolation. 

Alternatively set DAC to multiple of 176.4KHz 

--- Quote End ---  

 

 

 

Actually it is not 176.4 KHz... I changed it later to be multiple of 100 MHz and forgot :P It's 178.571 KHz 

 

 

--- Quote Start ---  

There is also issue of using different clock rates on FIR and CIC. Do you need that. You better use same system clock or it may go wrong 

--- Quote End ---  

 

 

I thought I have to clock the CIC with the required output sampling rate, that is 10 MHz. 

Actually, after the succes I got in SignalTap, I went back to ModelSim to simulate the design as is. But I got a totally different and strange output: 

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=10282&stc=1  

 

I tried to use same system clock for both IPs as you mentioned... nothing changed except the output of FIR was distorted and CIC gave exactly the same 

output of FIR.
Altera_Forum
Honored Contributor I
46 Views

1) If you are going to mix at 10Mhz then you need to upsample(interpolate) to 10MHz. 

2) 10000KHz/178.571KHz is a weird fraction and = 10000000/178571 that I doubt if it simplifies any further. 

Then you have to interpolate by num/8 (8 done in rrc) and decimate by denum. 

 

I don't know if your cic will support that sort of figure. 

 

3) use system clock of 10MHz on both fir and cic with a fifo in between to control rate. 

You cannot run cic output at 10MHz unless you upsample to 10MHz through FIR+CIC 

 

Who decides 178.571KHz. Is't an audio application?
Altera_Forum
Honored Contributor I
46 Views

 

--- Quote Start ---  

1) If you are going to mix at 10Mhz then you need to upsample(interpolate) to 10MHz. 

--- Quote End ---  

 

 

I am going to mix at 100 MHz, 10 MHz is just an intermediate frequency, I think I am going to use a compensation filter with interpolation factor of 10. 

 

 

--- Quote Start ---  

2) 10000KHz/178.571KHz is a weird fraction and = 10000000/178571 that I doubt if it simplifies any further. 

Then you have to interpolate by num/8 (8 done in rrc) and decimate by denum. 

 

I don't know if your cic will support that sort of figure. 

--- Quote End ---  

 

 

What I actually did is that I divided the 50 MHz by 280, I didn't write all of the resultant fraction but it exists in hardware. So I don't think I'll need fractional interpolation, or will I? 

 

 

--- Quote Start ---  

3) use system clock of 10MHz on both fir and cic with a fifo in between to control rate. 

You cannot run cic output at 10MHz unless you upsample to 10MHz through FIR+CIC  

--- Quote End ---  

 

 

How do I upsample through FIR+CIC? I didn't get this. 

 

 

--- Quote Start ---  

Who decides 178.571KHz. Is't an audio application? 

--- Quote End ---  

 

 

I did :D I chose to send audio over air for demonstration purposes.
Altera_Forum
Honored Contributor I
46 Views

I am a bit lost between figures. (10MHz,50MHz,280,100MHz).  

 

if your symbol rate is 50000/280 then you don't need fractinalupsampler 

 

you need to go up from 50000/280 to 100000 = 560 

 

8 in rrc, 10 in comp filter, 7 in cic 

 

well just use a fir interpolator at 70 or two firs at 10 and 7 

or rrc to go up by 56, fir by 10
Altera_Forum
Honored Contributor I
46 Views

Yes that's what I'm going to do. 

But do you know why ModelSim simulation failed to give correct CIC output? It's the same design... nothing changed.
Altera_Forum
Honored Contributor I
46 Views

I figured it out... reset signal of the CIC was going high before any clock edge rises. 

Do not you just love this view :D 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=10294
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