FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6359 Discussions

FIR coefficient reloading problem

Altera_Forum
Honored Contributor II
1,667 Views

I have a simple single rate FIR filter (StratixII, fully parallel, coef storage in M512, signed binary, 12 bit input data, 12 bit coefficient). 

I calculated a low pass with an external software, scaled the values to 12 bit (-2048 ... +2047) and imported the coefficient set with FIR-Compiler (I selected "no scaling"). That works fine :)  

Now I took the same coefficient set, made a coefficient reordering with 

coef_seq.exe coef_in.txt coef_reload.txt PAR M512 MSYM 12 1 SGL 1 12 

and loaded these parameters via the coef_in port. Then I see a strange signal (sinus input, viewing the output with an oscilloscope). It seems the amplitude is much to high an I have an overflow inside the FIR. I then scaled the values only to -256...+255 before reordering and it looks better. I can see the low pass characteristic but the amplitude is still to high and the signal little corrupted. 

 

As the low pass filter with the FIR-COMPILER imported values after reset work fine the calculated and scaled values should be OK. By the way when switching scaling from AUTO to MANUAL I see the factor 1.0.  

 

So I can imagine only two problems. 

1) coefficient reordering does fail 

2) reloading timing does fail (coef_we is active 1 clk before the first coefficient (0) and valid until the last coefficient (no delay)). 

 

I have attached screenshots from FIR-Compiler and the scaled and reordered coefficients. 

 

Has anyone an idea?
0 Kudos
6 Replies
Altera_Forum
Honored Contributor II
496 Views

If my coefficients are already in fixed point format, I would not scale them again in the GUI. Then 12-bit data_in with 12-bit coefficients give me 26-bit full resolution. 

 

What happens if you use FIR full resolution output? I normally scale out of the FIR boundry for better control and it works fine.
0 Kudos
Altera_Forum
Honored Contributor II
496 Views

Hi nemo, 

I have some news. I decreased the number of coefficients from 51 to 3 and everything was fine. So I increased the coefficients to 31 and also, everything is fine. As I have a logic analyzer on the coef_in port I'm sure that I'm loading all data, with 31 coeffs as well as with 51 coeffs. 

I suppose that coef_seq.exe has a bug. I tried to understand the source coef_seq.cpp but it is difficult. When having less or equal 31 coefficients, I always get a number of values from coef_seq.exe which are a power of 2 (4, 64, 128). With 51 coefs I get 192.  

 

As I already mentioned, when loading the coefficients with the GUI, it's OK. I think they will use coef_seq.exe also inside the GUI when transforming the coefficients!?! 

 

I'm trying to get an answer from ALTERA support because I can do nothing at the time because I don't know anything about the function of coef_seq.exe.
0 Kudos
Altera_Forum
Honored Contributor II
496 Views

I have a problem. In my project I can't overwrite a new coefficient set when coef_we is high, and so I can use only the precalculated set. Can you help me?

0 Kudos
Altera_Forum
Honored Contributor II
496 Views

Although this thread is stale by almost a year, I was wondering if anyone has had any luck (good or bad) with the coefficient reloading. I am currently working on a design that requires an 11-tap FIR filter that's re-loadable using the coef_in and coef_we ports. I have tried using the coef_seq program, and my 11 coefficients turn into 64 when I run the script, and I'm wondering why this is the case. I'm basically taking 11 values (already scaled) and running the following: 

 

>coef_seq coef.txt coef_mod.txt PAR M512 MSYM 18 1 SGL 1 18 

 

At least, in the example that Altera provides (using a 40-tap filter), the number doubled, which still isn't real intuitive, but at least it's not more than 4x. 

 

http://www.altera.com/support/examples/verilog/ver-fir-coefficient.html 

 

I was hoping to use this example, but my flavor of Modelsim AE is VHDL-only, so I couldn't get a good look at how the timing of the coef_in and coef_we signals was looking, because it's Verilog-based. The FIR Compiler datasheet gives a good enough description, but doesn't provide much insight to where to place, for example, a scaled 18-bit coefficient into a data bus that's 21-bits wide (which is another question that I've got). 

 

My most recent stab at simulating this has me instantiating my coefficient reload VHDL module into a DSP Builder .mdl and then trying to view the results of the coefficient reload "real time" in Simulink, but it's not exactly working as I had hoped. I also tried bringing the FIR filter in Modelsim, but I had too difficult of a time getting all of the proper libraries loaded (each time I found one that was missing, it called another library that either wasn't there or encrypted). 

 

Anyways, I don't have a really specific question, other than wondering if anyone's got this figured out. 

 

Jeff
0 Kudos
Altera_Forum
Honored Contributor II
496 Views

Hello, 

 

I have a problem. I have a FIR with 64 coefficients and i want to reload the coefficient set (i have just one coefficient set). I use the program coef_seq.exe but in out of this programm i have 416 coefficients. I don't undestand why?? If you can help me.... 

Thank you very much
0 Kudos
Altera_Forum
Honored Contributor II
496 Views

Hi, 

I try to remember....:confused:  

coef_seq.exe "converts" the coefficients to another type of data required for the ALTERA FIR function. Therefore also the number of data (no longer coefficients!) is changing.
0 Kudos
Reply