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Altera_Forum
Honored Contributor I
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FOC algorithm in Drive-On-A Chip reference design

Hello all, 

 

sorry if this is not supposed to be posted here. 

 

 

I have three questions regarding to the FOC algorithm implemented in the reference design mentioned in this post's title. 

1) About inverse-Clark transformation (or SVM) 

In the datasheet of the reference design, FOC algorithm is realized in hardware part, not in software part like Nios II nor MCU. 

So the hardware's final output is supposed to have Va, Vb, Vc. 

However the output of FOC algorithm in the reference design does NOT have them  

BUT has Valpha and Vbeta meaning that the algorithm does not do inverse-Clark transformation (am I right?). 

 

so who does the inverse-Clark transformation in the reference design? 

 

2) About FOC algorithm in software part 

The software included in the reference design also include FOC algorithm. 

As mentioned above, the datasheet says FOC algorithm is realized in hardware part. 

Why does the software also include FOC algorithm? 

 

3) About axis_in 

Why is its bit width is 8? 

In the datasheet, this reference design can handle up to 4 axis. 

So I think the width does not have to be more than 4. 

Why does it have more than 4? 

 

 

Sincerely, 

yhatagishi
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Altera_Forum
Honored Contributor I
95 Views

I found answers in the newest document. 

 

as for 1), inverse-Clarke transformation is not included somehow. 

as for 2), FOC is done by software to compare the result obtained by hardware and by software. 

as for 3), my guess is that it is 8 bits because there is no data type for 4 bits data. (char is 8 bit)
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