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I'm using DP83867 (Ethernet physical layer trans-receiver.) and cyclone V 5CEFA7F27I7 FPGA.
i can able to see the LED glowing at trans-receiver IC and RJ45 port when ethernet cable is connected at RJ45 port. after dumping the .sof file to FPGA.
I'm getting the error at Nios ii console as :
TSEMAC SW reset bit never cleared!
[tse mac init] Error: Incompatible 2 value with TX_CMD_STAT register return TXshift16 value.
I've attached the out snapchat to this post. and
I've attached the .qsys file and .bdf file to this post.
i cant able to get, where I'm facing the issue. please help me to find out.
Thank You,
Prajwal RJ
Edit: for the block in the .bdf file i've used the code as
--------------------------------------------------------------------------------------
--for eth_phy_reset
o_eth_tx_err <= i_gmii_tx_err WHEN(i_eth_mode = '1') ELSE i_mii_tx_err;
o_eth_tx_data <= i_gmii_eth_tx_data WHEN(i_eth_mode = '1') ELSE "0000" & i_mii_eth_tx_data;
o_eth_tx_clk <= i_gtx_clk WHEN(i_eth_mode = '1') ELSE i_phy_clk;
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Hi,
It looks like the error "TSEMAC SW rest bit never cleared" was given by the software driver in your design when you try to do software initialization for your design. Have you check the driver and found the reason?
Best regards,
zying
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Thank you for your Advises,
At software driver for the error "TSEMAC SW rest bit never cleared"
i found the code as,
--=======================
x=0;
while(IORD_ALTERA_TSEMAC_CMD_CONFIG(tse[iface].mi.base) &
ALTERA_TSEMAC_CMD_SW_RESET_MSK) {
if( x++ > 10000 ) {
break;
}
}
if(x >= 10000) {
dprintf("TSEMAC SW reset bit never cleared!\n");
}
--=========================
* ALTERA_TSEMAC_CMD_SW_RESET_MSK is defined as (0x2000) .
* IORD_ALTERA_TSEMAC_CMD_CONFIG(base) is defined as IORD_32DIRECT(base, 0x8)
* and tse, iface, mi are just defined in a structure.
kindly Please help me to fix this Problem.
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Hi,
Will you please help to read out the following registers when this error occurs?
- MAC registers: Rev (0x0), command_config(0x2)
- PCS registers: control(0x0), status(0x1)
Best regards,
zying
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Hi,
Is there any update from your side?
Best regards,
Zying
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Hi,
Since no hear any feedback from you, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.
Best regards,
zying
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I have added a 2k ohm pull-up resistor to Pin No. 21 of the PHY IC (MDIO pin).
In the QSYS file, I have enabled the "Align Packet Headers to 32-bit Boundary" checkbox in the "Triple-Speed Ethernet" IP. After making these changes, the error previously appearing in the Nios II console output has been resolved. The current screenshots of the Nios II console window is attached.
However, when attempting to ping, I am still encountering the "Request Timed Out" error in the command prompt, and I have included a screenshot of this issue as well.
I would appreciate any guidance you can provide to resolve this remaining issue.
Thank you for your support.
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Hi,
I have an update regarding the loopback test:
Code Overview
In the Main_Code file, I implemented the loopback test as follows:
=====================================================================
void ethernet_loopback_test() {
// Initialize TSE and PHY
InitNetwork(); // Initialize the Triple-Speed Ethernet (TSE) IP
printf("TSE initialized.\n");
printf("PHY internal loopback mode configured.\n");
// Prepare Ethernet packet (64 bytes)
uint8_t tx_packet[64] = {
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, // Destination MAC (broadcast)
0x00, 0x07, 0xAB, 0xF0, 0x0D, 0xBA, // Source MAC (example)
0x08, 0x00, // Ethertype (IPv4)
0x45, 0x00, 0x00, 0x2E, // IPv4 header (first bytes, rest as padding)
0x00, 0x00, 0x40, 0x00, 0x40, 0x11, // More IPv4 header
0xB8, 0x61, // Checksum (placeholder)
0xC0, 0xA8, 0x00, 0x19, // Source IP (192.168.0.25)
0xC0, 0xA8, 0x00, 0x1A, // Destination IP (192.168.0.26)
// Rest of the payload (padding for simplicity)
0xDE, 0xAD, 0xBE, 0xEF, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
// Transmit packet
tse_mac_sTxWrite(tx_packet, sizeof(tx_packet));
printf("Packet transmitted.\n");
// Receive looped-back packet
uint8_t rx_packet[64] = {0}; // Initialize the receive buffer with zeros
tse_mac_aRxRead(rx_packet, sizeof(rx_packet));
printf("Packet received.\n");
// Compare transmitted and received packets
if (memcmp(tx_packet, rx_packet, sizeof(tx_packet)) == 0) {
printf("Loopback test successful! Packets match.\n");
} else {
printf("Loopback test failed. Packets do not match.\n");
}
}
=============================================================
Additionally, in the Altera_Avalon_tse.h file, I enabled the PHY loopback for debugging purposes by setting:
#ifndef ENABLE_PHY_LOOPBACK
#define ENABLE_PHY_LOOPBACK 1
#endif
Observations
After making these changes, the Nios II console output displays "Putting PHY in Loopback," followed by the warnings "WARNING: TX SGDMA Timeout."
I've attached a screenshot ("Nios II - Debug - Screenshot -1") for reference.
Further Analysis
I noticed that the Tx enable signal and the Tx data signal remain at "0" (both in and out of loopback mode). During debugging, I found that the Tx_clock from the PHY IC is fixed at 2.5 MHz, regardless of the speed configured in the Nios II software.
Interestingly, the Rx_clock changes correctly when I adjust the Ethernet speed settings on the PC (2.5 MHz, 25 MHz, 125 MHz, etc.). The data is also successfully captured in Signal Tap during a ping operation, indicating no issues on the receiving side or with the hardware design.
The problem seems to be on the transmitting side, where we are unable to configure the PHY IC correctly.
I would greatly appreciate your assistance in troubleshooting this Tx_clock issue. Please help me resolve this problem. I've also attached the project folder link for your reference.
Thank you for your support!

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