FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6359 Discussions

Failure to restore DDR3 UniPHY Qsys example

Altera_Forum
Honored Contributor II
‎09-07-2012 01:26 AM
849 Views

I've downloaded a 8-Bit Wide DDR3 UniPHY-Based Qsys example from Altera website: 

http://www.altera.com/support/examples/verilog/ver-stratix-iv-8-bit-ddr3-uniphy-qsys.html 

 

Trying to open the archive emi_uniphy_ddr3_siv_qsys.qar results in the following errors: 

 

 

Error: Failed to restore: uniphy_ddr3_qsys/synthesis/submodules/uniphy_ddr3_qsys_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper.v Error: Failed to restore: uniphy_ddr3_qsys/synthesis/submodules/uniphy_ddr3_qsys_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_ociram_default_contents.mif 

 

Looks like at least a couple of files are missing in that archive.  

 

Any quick solution to this ? 

 

Thanks, 

Evgeni
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎09-10-2012 05:10 PM
160 Views

I opened a service request with Altera, and they gave me a different QAR file that works with quartus rev 11.1sp2. 

 

It's attached. 

 

Thanks, 

Evgeni
ddr3_qsys_111SP2.qar
0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.