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Altera_Forum
Honored Contributor I
724 Views

Failure to restore DDR3 UniPHY Qsys example

I've downloaded a 8-Bit Wide DDR3 UniPHY-Based Qsys example from Altera website: 

http://www.altera.com/support/examples/verilog/ver-stratix-iv-8-bit-ddr3-uniphy-qsys.html 

 

Trying to open the archive emi_uniphy_ddr3_siv_qsys.qar results in the following errors: 

 

 

Error: Failed to restore: uniphy_ddr3_qsys/synthesis/submodules/uniphy_ddr3_qsys_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper.v Error: Failed to restore: uniphy_ddr3_qsys/synthesis/submodules/uniphy_ddr3_qsys_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_ociram_default_contents.mif 

 

Looks like at least a couple of files are missing in that archive.  

 

Any quick solution to this ? 

 

Thanks, 

Evgeni
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Altera_Forum
Honored Contributor I
35 Views

I opened a service request with Altera, and they gave me a different QAR file that works with quartus rev 11.1sp2. 

 

It's attached. 

 

Thanks, 

Evgeni
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