Fitter can't place ATX PLL on Stratix 10

[Vladimir_Y_Intel]

I am building a system with Stratix 10. My intention is to make it work on 20Ghz datarate.

I used Platform Programmer in Quartus to create PHY and surrounding blocks like reset control, etc.

After adding and connecting ATX PLL, this is what I get:

Error (14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (1 HSSI_TX_CHANNEL_CLUSTER(s), 1 HSSI_CR2_PMA_LC_PLL(s)). Fix th

e errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this perip

hery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search f

or this specific error message number.

    Error (175001): The Fitter cannot place 1 HSSI_CR2_PMA_LC_PLL, which is within L-Tile/H-Tile Transceiver ATX PLL Intel Stratix 10 FPGA IP top_xcvr_atx_pll_s10_htil

e_0_altera_xcvr_atx_pll_s10_htile_180_sogaeya.

        Error (16234): No legal location could be found out of 6 considered location(s). Reasons why each location could not be used are summarized below:

            Error (175006): There is no routing connectivity between the HSSI_CR2_PMA_LC_PLL and the HSSI_CR2_PMA_LC_PLL

                Error (175022): The HSSI_CR2_PMA_LC_PLL could not be placed in any location to satisfy its connectivity requirements

    Error (175020): The Fitter cannot place logic HSSI_TX_CHANNEL_CLUSTER that is part of L-Tile/H-Tile Transceiver Native PHY Intel Stratix 10 FPGA IP top_nphy_altera

_xcvr_native_s10_htile_180_eqiroqq in region (0, 70) to (2, 134), to which it is constrained, because there are no valid locations in the region for logic of this type.

        Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:

            Error (175005): Could not find a location with: HSSI_CHANNEL_TYPE of HSSI_CHANNEL_TYPE_GX (1 location affected)

Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.

Error (16297): An error has occurred while trying to initialize the plan stage.

How do i fix it?

Thanks,

Vladimir.

[crclayton]

I can't speak to your situation, but for people coming across this in the future -- I had this same issue with the Stratix 10 GX SI Development Kit, and I switched my QSFP28 from IF0 to IF1 and the issue went away.

#QSFP28 IF1

set_location_assignment PIN_AK49 -to o_tx_serial[0]

set_location_assignment PIN_AL47 -to o_tx_serial[1]

set_location_assignment PIN_AJ47 -to o_tx_serial[2]

set_location_assignment PIN_AF49 -to o_tx_serial[3]

set_location_assignment PIN_AL43 -to i_rx_serial[0]

set_location_assignment PIN_AH45 -to i_rx_serial[1]

set_location_assignment PIN_AF45 -to i_rx_serial[2]

set_location_assignment PIN_AG43 -to i_rx_serial[3]

set_location_assignment PIN_AM38 -to i_clk_ref

#QSFP28 IF0

#set_location_assignment PIN_BD49 -to o_tx_serial[0]

#set_location_assignment PIN_BA47 -to o_tx_serial[1]

#set_location_assignment PIN_AW47 -to o_tx_serial[2]

#set_location_assignment PIN_AY49 -to o_tx_serial[3]

#set_location_assignment PIN_BA43 -to i_rx_serial[0]

#set_location_assignment PIN_BB45 -to i_rx_serial[1]

#set_location_assignment PIN_AY45 -to i_rx_serial[2]

#set_location_assignment PIN_AU43 -to i_rx_serial[3]

#set_location_assignment PIN_AM41 -to i_clk_ref