I have a problem with Folded design. My sample rate is clock_rate/16. So if a I have a counter inside this block, I expect one step after every 16 clock cycles. From DSP Builder manual, I understood, that I should make a design as for unfolded case. In reality, after 16 clock cycles I have 16 steps higher value. How is that in the end? Is sequential blocks are different maintained than e.g. delays? And what if I set ChannelIn folding to 16, and ChannelOut folding disabled. Does it read inputs as "latched" at every 16th cycle and process them every single cycle? Kamil.