Unfortunately, we don’t have the descriptions about byte-write limitations in Arria 10 DDR3 IP and I apologize for the inconvenience caused.
In general, one data mask (DM) pin exists per DQS group. Below is the example for x8 DDR3 interface.
So, for x64 interface, you will have total of 8 DM pins/bits. DM needs to be a differential pin-pair with a DQ pin due to the FPGA architecture. This pinout requirement is documented in the EMIF pinout guidelines. In the EMIF Handbook Volume 2, chapter 1.2.1 on page 40, it states :
"13.Ensure that DM/BWS pins are paired with a write data pin by placing one in an I/O pin and another in the pairing pin for that I/O pin. It is recommended—though not required—that you follow the same rule for DBI pins, so that at a later date you have the freedom to repurpose the pin as DM." => https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_plan...
I sincerely hope this helps.
My mistake... the question I had is Avalon related, not hard memory controller. I was looking for the following:
When more than one bit of the byteenable
signal is asserted, all asserted lanes are adjacent.
The number of adjacent lines must be a power
of 2. The specified bytes must be aligned on an
address boundary for the size of the data. For
example, the following values are legal for a 32-
• 1111 writes full 32 bits
• 0011 writes lower 2 bytes
• 1100 writes upper 2 bytes
• 0001 writes byte 0 only
• 0010 writes byte 1 only
• 0100 writes byte 2 only
• 1000 writes byte 3 only
My Avalon interface is 256-bits wide (32 byte enables) and I was looking for the rules on how to use them correctly.
Thanks for replying,
Basically the concept is the same for 256 bits. If you need to write full data the set all the byte enable to '1' . It depends on which data you want to write. I demonstrate it in below table for example.