GPIO DDRIO IP output swapped: datainhi/datainlo inverts forwarded clock

[pnp]

I have a source-synchronous interface for which I am forwarding a clock with a DDRIO register as recommended in AN433 pp6-7 to minimize skew between the clock and data waveform:

I created a GPIO IP in Quartus Prime Pro 21.1 to forward the clock:

and instantiate as follows:

module ddriotest
(
    input logic  clk,
    output logic clk_fwd,
    output logic [7:0] data
);
    // forward clock
    ddr_output i_ddr
    (
        .ck(clk), .din(2'b10),
        .pad_out(clk_fwd)
    );

    // generate example source synchronous output data
    logic [7:0] count = '0;
    always @(posedge clk) count <= count + 1'b1;
    always @(posedge clk) data <= count;
endmodule

When I look at the post-fitter technology map netlist, I see DATAINHI = 1'b1 and DATAINLO = 1'b0 on the DDIO_OUT primitive, which matches the connections shown in AN433 to forward the clock (see pic above for comparison):

But when I simulate this project, I see:

Notice that clk and clk_fwd are inverted with respect to one another! I believe they should be in-phase aside from Tco delay and clock delay, and both of those delays wouldn't be present in this functional sim. I have to swap  din[0] and din[1]to get desired behavior. I have good reason to believe this is happening with the actual hardware as well, so it isn't just a sim issue. I've followed the connection all the way to the cyclone10gx_ver.cyclone10gx_ddio_out primitive, which is encrypted so I can't look any further.

Why is this inversion taking place?

I'm using Quartus Prime Pro 21.1 and GPIO IP 20.0 with Questa Intel Starter Edition-64 21.1 (beta) for a Cyclone 10 GX device. Full example project and sim attached.

Thanks,

Paul

[pnp]

Looking at the very bottom of ug_altera_gpio.pdf there is this note:

I feel like this is a clue, though this paragraph is as clear as mud to me. In my case I did not migrate the IP, I am not using the legacy top-level port names,  and the port meaning in that bullet list is what I expect the IP to do.

[AminT_Intel]

Hello,

What do you mean by 'I have good reason to believe this is happening with the actual hardware as well, so it isn't just a sim issue'?

Thanks

[pnp]

The synthesized design behaves as the simulation shows: the signal on datainhi is output on the falling edge of the clock. For my source synchronous interface, this was sneaking in a 180-degree phase shift on the output clock. The timing analyzer assumes pos-unate edges so data transitions occur in the wrong place relative to the active edge of the clock, which breaks my interface. If I swap datainhi and datainlo, my design works as expected.

[AminT_Intel · Accepted solution]

Hello Paul,

We have checked the design. We think it may be because of your coding design. We switched your 10 to 01 and got this result. Is this what you are expecting?

Image 1: Waveform

Image 2: Design

Image 3: Reference from https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_gpio.pdf

Thank you.

[pnp]

Amin,

Thank you for looking into this issue! That is exactly where I ended up: I swapped the din values as you did. I see the waveform you posted from the documentation, but that is for half-rate conversion. We are not doing half-rate conversion in this case.

My issue is that the behavior contradicts the documentation:

from https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_gpio.pdf

In this case, datain_width is 1. So

datain_h = din[(2 * 1 - 1):1] = din[1:1] and

datain_l = din[(1 - 1):0] = din[0:0]

which matches what I see in the technology mapped netlist (see my initial post in this issue). The comment at the end of the document states:

which is what I expect to happen, however swapping values in din is required to get the expected behavior.

Thanks,

Paul

[AminT_Intel]

Hello,

The last screenshot you've given is on Guideline: Swap datain_h and datain_l Ports in Migrated IP which is for migration for your GPIO IP from previous devices to the GPIO IP core. This only applies only for the migration.

[pnp]

Amin,

I am grateful for your assistance in resolving this issue: all of our cyclone10gx_ddio_out  instances are working properly now in our FPGA design. I accept that I have misunderstood the documentation and that the GPIO IP is working as Altera designed. I'd suggest, though, that it would be helpful if someone added a full-rate scenario timing diagram to the docs, because the IP does behave differently than the legacy altddio_out megafunction with nearly identical port names.  At the very least, this thread will be here if anyone else is snagged.

Best regards,

Paul

[AminT_Intel]

Hello Paul,

I'm glad that it helps! Thank you for the suggestion we will take note of that.

Thanks

[AminT_Intel]

 I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.