GTS Transceiver PHY - Reference Clock Network

[K606]

I am trying to understand the GTS Clocking Network.

In the user guide doc here, it is possible to see the following suggested design:

However later in the doc, we can see this statement:

Which is a confusing suggestion, as it suggests an the input clock to the SysPLL should control the i_rx_cdr and i_tx_pll.

Is there somewhere else that explicitly explains how to connect these three regional/local-ref clocks? Are they all connected to the same reference clock?

Many Thanks,

Kai

[Ash_R_Intel · Accepted solution]

Hi,

The figure is just showing them as open ports available for connections from the architecture perspective. The suggestion is asking to connect those inputs to the same source in an actual design.

Please always follow the suggestion.

Regards

[Ash_R_Intel]

Thanks for accepting my reply. As the query has been answered, I am setting the case to closure. However, it will be open for other community members to comment on.

Regards