FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5950 Discussions

GXB tranceiver pll lock not stable

Altera_Forum
Honored Contributor II
953 Views

Hi 

 

I'm trying to get a low latency 10g XFP tranceiver to work. I'm using the Mega Wizard in Quartus II 11.1sp2 to create this core and the reconfigure core. Both have been synth'ed and there are no errors.  

 

However I've connected all the Locked signal from all PLL's to output LEDs on my dev board and my two primary PLL's goes into lock just fine however the lock signal from the low latency gxb core blinks (IE its not stable) I've tested my refclock and its the right value and stable. I've tryed to reset the core following the documentation (I'm using the internal reset core). I've tryed with both CMU and ATX pll (I had no luck with the ATX pll what so ever). 

 

I can see the tx and rx ready signals also goes on and off following the lock signal somewhat.  

 

My CMU refrence frequency is 155.52MHz and the internal tranciever frequency should be 9953.28MHz. 

 

I'v read the documentation on this core alot however i thinks its a bit vague.  

 

I dont know if i need to supply more information than this.  

 

regards Anders
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
78 Views

I have solved this my self

Reply