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Honored Contributor I
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Gen1x1 PIPE error during Place and Route (Fitter) due to tx_pma_div_clkout factor

Hi, 

 

I have summarized the background about my design and Hardware setup in next two paragraphs and the issue I'm facing is in remaining paragraphs. 

 

I'm trying to implement Gen1 PCIe (3rd Party IP) on Altera Arria 10 (10AX115S2F45I1SG) GX Board. The configuration on my controller interfacing with PIPE side is 1 lane and 32 bit operating at 62.5MHz ( this will be supplied from PHY). But since the Altera PHY PIPE doesn't support 32bit, I'm trying to generate PIPE with 16 bit at 125MHz, so that I can use some logic to convert from 16bit @125MHz to 32bit @ 62.5MHz for the controller. 

 

I am able to generate PIPE Gen1x1 successfully using Quartus 15.1.2 by following the "Native PHY IP Parameter Settings for PIPE" suggested in the Arria 10 Transceiver manual. During configuring the PIPE in Quartus, I have enabled the option to include "tx_pma_div_clkout" port and set "tx_pma_div_clkout division factor as 2" so that I can supply 62.5MHz to my controller. 

 

When I tried to run the Fitter, I get the following error: 

error (15653): the fitter cannot find a legal configuration for the following atoms. update any outdated transceiver phy ip cores, correct any illegal pin assignments, and then recompile your design. 

error (15744): the settings must match one or more of these conditions: 

error (15744): ( ( datarate_bps > 4999999999 ) or ( rser_clk_divtx_user_sel == divtx_user_off )) 

error (15744): but in atom 'pipe_gen1_x1_native_ip<img src="images/smilies/tongue.png" border="0" alt="" title=":p" smilieid="5" class="inlineimg">ipe_gen1_x1|pipe_gen1_x1_native_ip_altera_xcvr_native_a10_151_o255bgq:xcvr_native_a10_0|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pma_rev_20nm5:inst_twentynm_pma|gen_twentynm_hssi_pma_tx_buf.inst_twentynm_hssi_pma_tx_buf' 

error (15744): the following assignments violate the above conditions: 

error (15744): xtx_path_datarate = 2500000000 

error (15744): but in atom 'pipe_gen1_x1_native_ip<img src="images/smilies/tongue.png" border="0" alt="" title=":p" smilieid="5" class="inlineimg">ipe_gen1_x1|pipe_gen1_x1_native_ip_altera_xcvr_native_a10_151_o255bgq:xcvr_native_a10_0|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pma_rev_20nm5:inst_twentynm_pma|gen_twentynm_hssi_pma_tx_ser.inst_twentynm_hssi_pma_tx_ser' 

error (15744): the following assignments violate the above conditions: 

error (15744): ser_clk_divtx_user_sel = divtx_user_2 

error (12274): a critical error occurred while the periphery placement was committed to the atom netlist. the atom netlist is now invalid and the fitter must be restarted. 

 

 

Since my design uses 2.5Gbps rate I ignored "xtx_path_datarate = 2500000000" error. But I observed that the error is due to "ser_clk_divtx_user_sel = divtx_user_2" and this is because I have set "tx_pma_div_clkout division factor" as 2 as this can give me required 62.5MHz clock for my 32bit controller interface and make the PIPE lane width as 16bit @ 125MHz. Though this setting is valid as per Native PHY settings suggested in Transceiver model, I'm unable to do run Fitter. I do not observe this error when I disable division factor. 

 

Any suggestions to fix this issue? 

Thanks in advance. 

 

pcs
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