FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Glitch less clock

ymiler
Employee
1,171 Views

Hi

 

I need to implement multiplexer between 2 async clocks
there is a flag that should choose between them
This code can cause to glitch clock and I'd like to avoid from it

 

I can't use the "clock control Intel FPGA IP" since this option doesn’t enable for my device - Stratix 10 -1SM21BHU2F53E2VG

ymiler_3-1670856763825.png

 

other option is implement the following :

 

ymiler_4-1670856885509.png

but , the tool report that it's unsupported cascaded clock so that tool can't convert it.

 

Do you idea how can I solve this issue ?

 

Yishay

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13 Replies
sstrell
Honored Contributor III
1,159 Views

Doesn't the clock control block have an enable signal option?  Can't you use that?

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ymiler
Employee
1,155 Views

According to this page :

https://www.intel.com/content/www/us/en/support/programmable/articles/000076600.html

 

only part of the devices have this option :

 

ymiler_0-1670876807949.png

 

Indeed , the Quratus message is :

 

ymiler_1-1670876913813.png

But , I get same message in newer Quartus version 

 

 

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Nurina
Employee
1,131 Views

Hi,


Sorry for the late response. Can you share the .qar file here?


Regards,

Nurina


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ymiler
Employee
1,120 Views

sure ,

 

Please send me pointer to secure share location 

 

 

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ymiler
Employee
1,114 Views

pointer to secure and Intel Only Access.

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Nurina
Employee
1,101 Views

Hi,


You may share the design through email. I'll send you an email right now.


Regards,

Nurina


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Nurina
Employee
1,022 Views

Hi Yishay,


I suggest you use the enable signal available in the IP. Is there any reason why you cannot use this?


Regards,

Nurina


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ymiler
Employee
1,017 Views

 

Hi Nurina,

 

As I wrote in the top of this case I cant enable this signal since this option doent available 

ymiler_0-1672127883547.png

Yishay

 

 

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sstrell
Honored Contributor III
994 Views

We're not talking about that option.  Scroll down.  Under "Clock Gating", use the enable options there.

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ymiler
Employee
984 Views

OK ,

 

I see what you are taking about ,

But , how  this option can solve the glitch less issue ?

 

ymiler_0-1672176509725.png

I need the switchover option :

ymiler_2-1672176683720.png

 

 

 

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Nurina
Employee
969 Views

Hi,


As mentioned in this KDB https://www.intel.com/content/www/us/en/support/programmable/articles/000076600.html

You can prevent glitches during clock switchover by using the ena port.


The ensure glitch free clock switchover option is not available in any of the Clock Control IP for Stratix 10 at the moment unfortunately, so you'll have to use clock enable : https://www.intel.com/content/www/us/en/docs/programmable/683195/20-3/ip-core-parameters-29948.html


Regards,

Nurina


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ymiler
Employee
958 Views

Hi 

 

Thank you 

 

I will use it , this is a good workaround .

 

Yishay

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Nurina
Employee
947 Views

Hi,


I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey


Regards,

Nurina


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