I need to implement multiplexer between 2 async clocks
there is a flag that should choose between them
This code can cause to glitch clock and I'd like to avoid from it
I can't use the "clock control Intel FPGA IP" since this option doesn’t enable for my device - Stratix 10 -1SM21BHU2F53E2VG
other option is implement the following :
but , the tool report that it's unsupported cascaded clock so that tool can't convert it.
Do you idea how can I solve this issue ?
According to this page :
only part of the devices have this option :
Indeed , the Quratus message is :
But , I get same message in newer Quartus version
As mentioned in this KDB https://www.intel.com/content/www/us/en/support/programmable/articles/000076600.html
You can prevent glitches during clock switchover by using the ena port.
The ensure glitch free clock switchover option is not available in any of the Clock Control IP for Stratix 10 at the moment unfortunately, so you'll have to use clock enable : https://www.intel.com/content/www/us/en/docs/programmable/683195/20-3/ip-core-parameters-29948.html
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