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Altera_Forum
Honored Contributor I
749 Views

HARD IP DDR3 with UniPHY + ArriaVGX: too long not local_ready

Hello! 

 

I am long enough work with DDR/DDR2/DDR3 IPs using Altera Device's. But this see first time. 

 

I use 2 chips together (32 bit width) Hard IP DDR3 600 MHz. And see that during long read write transactions local_ready signal may not ready up to 1.12 us (1400 tacts of 125MHz clock). I specially at first write RAM then read using bursts and do it repeatedly (in loop). And see these holes in ready very often... I have no any timing slacks after compilation. IP was created with megawizard. 

 

What is it? Refresh? Why is so long?  

Any suggestion?  

Please Help! )
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Altera_Forum
Honored Contributor I
28 Views

Problem has been solved. If change parameters to control refresh then local_ready nearly always ready (but refresh must be done every 4 us). In my case I don't do refresh at all because algorithm which works with RAM write and read from the start address to N address without delays (all needed rows are always charged). 

 

Goodluck to every one!
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