HARD IP PCIex STRATIX IV , DMA with data jumgled

[Altera_Forum]

Hi ,  

 I have a strange issue with a Stratix IV . I am using jungo PCIex driver and a stratix IV 70 (but i had the same problem with stratix IV 230 ).  I use the hard IP pciexpress generated by megawizard .  there are two cases : first one i transfer some data from PC to FPGA memory , that is ok , i can transfer a lot of data without problem , in fact the memory is a a kind of fifo , and i check the data integrity , just by having done a counter .  DW (n+1) = DW(n) +1 . So i know that all data have been transferred and with good integrity and in order. And i put a trigger into the FPGA able to detect if not ( DW(n+1) = DW(n) + 1;  Now , i do the same thing using the DMA , and i have something strange . I have got the good number of data , but they are jumbled ( out of order ) .  For example , during a transfer from 0x00000000 to 0x000000FF i will have 0x00000000 0x00001 , 0x2 0x3 0x4 , 0x5 ...... 0x3a,0x3b 0x3c , 0x40 , 0x41 , 0x42 ....0x50 .. 0x60... 0x70 ....... 0x7F , 0x3d,0x3e,0x3f , 0x80 , 0x81   The data received followed a sequence from 0x00000000-0x0000003C is 0x00000040h, missing the data from 0x0000003D-0x0000003F, only to appear after 0000007Fh.  i am getting the entire data which was sent from the application but it is coming out of order. how can i receive 0x3e and 0x3f after having received 0x7e,0x7f ????????  What i am sure is that data coming from PC are jumbled , i saw them with tap signal .  In two case , i am allocating the same buffer of 1kilobytes with a counter data. Payload size is 128 bytes     Does someone has had that yet ? Thanks