HDCP in "HDMI Intel FPGA user guide"

[Nagaraju478]

I haven't found any details in document "HDMI Intel FPGA user guide" about how HDCP encrypts and decrypts the video . I do have few questions below which needs to be addressed.

Question: As hdcp cipher(see hdcp v2.3 spec(HDMI)) encrypts/decrypts five pixel at a time, there could be a problem when partial pixels(less than 5 pixels, for example 3 pixels) left and when vsync asserts after few clock cycles. This can pause feeding the available 3 pixels to hdcp cipher till vsync asserts. How this situation is handled?

[Wincent_Altera]

Hi ,

May I know is there any specific FPGA device you are looking at ?

For Arria 10, you may found the information under https://www.intel.com/content/www/us/en/docs/programmable/683156/24-1-19-7-3/hdcp-over-hdmi-design-example-architecture.html

For detailed information about the HDCP over HDMI design examples, refer to the Intel® Arria® 10 and Intel® Stratix® 10 design example user guides.

Note: The HDCP feature is not included in the Intel® Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.

Let me know if that answered your question.

Regards,

Wincent_Altera

[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket. Nevertheless, you can still response to the forum and I will be available to assist you.

Regards,

Wincent_Altera

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[Wincent_Altera]

Hi

We have not hear from you and this Case is idling. It is not recommended to idle for a week.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

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Regards,

Wincent_Altera

p/s: If any answer from the community or Altera Support is helpful, please feel free to give the best answer or rate 9/10 survey.