HDL import - Multiple clock error

Altera_Forum · ‎03-26-2009

Hi,

I was trying to convert the DE2 i2sound example (found in the DE2 demonstrations) to a DSP builder model file using HDL import technique. But i'm having a problem with multiple clocks ( 2 internally derived clock). I can not understand what in wrong in here. I've attached the files. Please help.

thanks.

Omee

Altera_Forum · ‎03-27-2009

--- Quote Start ---

Hi,

I was trying to convert the DE2 i2sound example (found in the DE2 demonstrations) to a DSP builder model file using HDL import technique. But i'm having a problem with multiple clocks ( 2 internally derived clock). I can not understand what in wrong in here. I've attached the files. Please help.

thanks.

Omee

--- Quote End ---

Hi,

I try to run your project. I found out that the port list of your i2c_first.v does not fit to the component defintion.

I have the corrected project attached.

Kind regards

GPK

Altera_Forum · ‎03-27-2009

thanks for your kind reply!

Unfortunately, i still can not compile the project. It is showing some problem about internally derived clock, which i cannot understand :(

I tried to compile the design directly from matlab, but it was no success. Then, i created the project file only and tried to compile it form quartus II. It showed the internally derive clock problem.

Please help...

Altera_Forum · ‎03-30-2009

Could you quote the whole error message with any context there is?

Altera_Forum · ‎04-01-2009

Hello everyone,

I think i've solved the multiple clock related problem. As far as i've understood, if your verilog code has more than one signals whose edges triggers different events then in HDL import block, all these inputs are considered as clocks and the software tries to reduce them into a single clock. I think i've solve this problem in my code, i've now used only one clock and used logical operations to make the other clocks work.

Now i have only one problem. I've checked all the pins, inputs and outputs and the logic, but i don't know why my design is still not working :( I've only tried to implement a reduced form of the DE2_sound demonstration provided with the board.

Here is my files. Please help.......

thanks.

Altera_Forum · ‎04-01-2009

Hi Onee,

Did you simulate your HDL codes? According to your *.fit.summary report file, your design consists of only 2 registers. Many warning messages are reported in *.map.rpt informing most of registers are reduced due to stuck clock or clock enable.

EOFZ