FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5918 Discussions

HDMI Reference Design FR_CLK

JLee25
Novice
290 Views

Hi all,

  I am curious to know the requirement of this fr_clk mentioned in C10 GX HDMI UG, https://www.intel.com/content/www/us/en/programmable/documentation/ezu1511767661589.html.

 

My question is what frequency should be used for this purpose?

Can I use 100 MHz instead of this 625MHz?

As I noticed the design file use "300 MHz" instead of "625MHz"..

Please let me know.

Thank you!

 

BRs,

Johnson

0 Kudos
1 Solution
Deshi_Intel
Moderator
266 Views

HI Johnson,


On 2nd thought, I think you can still connect fr_clk while providing whatever clk frequency that's available on your board. Eg : 100MHz.


I found out more info. It should still works as stated from below A10 HDMI example design guideline doc that explained on fr_clk functionality.


Thanks.


Regards,

dlim


View solution in original post

4 Replies
Deshi_Intel
Moderator
282 Views

Hi,


fr_clk is the transceiver power on calibration pll refclk source for HDMI Tx and CDR refclk0 for HDMI Rx.


It's recommended to follow back example design to use 300MHz.


Thanks.


Regards,

dlim


JLee25
Novice
270 Views

Hi dlim.

  Thank you for the reply!

What bothers me is the clock did not exist in the old reference design..

And I have a design following the old without this fr_clk..

And it's not possible to add this as all the clock pins are used.

 

Therefore would you check if this fr_clk is a must?

BRs,

Johnson

Deshi_Intel
Moderator
267 Views

Hi Johnson,


Your understanding is correct.


This is new feature where we added in latest HDMI IP example design in case customer required quick transceiver power up calibration process.


If you don't have such concern then it's totally fine to ignore it.

  • Pls modify gxb_rx NativePHY IP to change default CDR refclk from 0 to 1
  • CDR refclk 0 is the FR_CLK that you want to bypass while CDR refclk 1 is the TMDS clk that HDMI is using


Thanks.


Regards,

dlim


Deshi_Intel
Moderator
267 Views

HI Johnson,


On 2nd thought, I think you can still connect fr_clk while providing whatever clk frequency that's available on your board. Eg : 100MHz.


I found out more info. It should still works as stated from below A10 HDMI example design guideline doc that explained on fr_clk functionality.


Thanks.


Regards,

dlim


Reply