FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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HDMI ip core not working at 1080p 60hz resolution


I am implementing the intel HDMI IP core on an arria 10 using dynamic reconfiguration. I am able to get all lower resolutions and higher resolutions to work except 1080p @ 60 hz with 148.5 Mhz pix clk. 1080p @ 30 hz works at 74.25,hz and 4k30 at 297mhz works. When it is not working all my pll's and transceivers are locked and outputting the correct freq as seen on a scope. the HDMI core vid_lock and locked outputs are all low.

Any ideas?

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HI, There are couple of things that you can try out 1) Try compile design with latest Quartus version to see if the issue go away. There could be some bugs that have been fixed with newer Quartus version 2) Have you try with HDMI example design instead ? https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an776.pdf 3) Have you validated to ensure HDMI IP VID clk and LS clk are configured correctly with the right frequency ? Thanks. Regards, dlim
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