FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

HIL block

Altera_Forum
Honored Contributor II
923 Views

When i am using HIL block only output port is generated not the input ports what should be the solution? plz reply

0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
244 Views

I don't know much about HIL, but you could try looking at the design examples, there's an example at 13-3 here: http://www.altera.com/literature/hb/dspb/hb_dspb_std_lib.pdf

0 Kudos
Reply