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HPCII for DDR2 problem: Clock and initialization always low

Altera_Forum
Honored Contributor II
806 Views

Hello everybody. I ask some help for the use of HPCII. I am using this megafunction in full mode, with a ref clock for the pll of 125 mhz and an "out clock" for the memory of 167mhz. I have desabled the calibration (I see this advise in other threads) and with this option the functional simulation works. 

When I run the gate simulation (post fitting) nothing happened (both with "skip calibration" and "quick calibration"). The signal "local_init_done" stay always low and so the "mem_clk_p" (the clock for the memory) and the auxiliary "phy_clk". 

Does somebody has some solutions or advises? 

 

I am using the HPCII (with altmemphy) to control a DDR2 Micron MT47H32M16CC-3 x4 + MT47H32M8BP-3 x1 with a CycloneIII EP3C120F780C7 (mounted on the EVB ). 

 

Thanks
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Altera_Forum
Honored Contributor II
114 Views

I tryed to use the HPCII with only one MT47H32M16CC-3 module, and all works fine, but if I use the megafunction with four MT47H32M16CC-3 modules and the MT47H32M8BP-3 module, the signal "local_init_done" is always low (I say it with the SignalTap). 

 

Could someone explain me what could be the problem? 

 

Thanks
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