Hard IP for PCIe gen 3 simulation on Arria 10

[Altera_Forum]

I've successfully run simulations of a gen 1 interface, but I am having real troubles doing a gen 3 sim. I'm using the Avalon streaming core for an endpoint application. I've created a testbench system through Qsys. When I run the simulation in ModelSim-Intel FPGA, I see the LTSSM states go through detect, polling, config, recovery, and then lo, but that's it. I see no activity on the streaming interface. I think I'm missing a driver for the root port BFM. For a gen 1 sim, I used the altpcietb_bfm_driver_chaining.v file from the DMA design example as the driver. I thought this same driver was included in altpcietb_bfm_rp_gen3_x8.sv automatically generated by Qsys. 

 I'm also not sure how to customize the testbench driver (if I can find it). All I want to do is try writing and reading BAR0, but I'm not sure where to put in the functions for this as they are described in the user guide.  I am not a PCIe expert by any means, so I'd appreciate any advice or hints anybody might have about doing this.

[Altera_Forum]

I'm coming back to this. I'm stuck in the LO state. I've tried adding my own config and BAR read/write tests to altpcietb_bfm_rp_gen3_x8.sv, but they never happen. I seem to be stuck in configuration. In the simulation messages, I see the link negotiated to x4. Maybe it's still trying to get to x8 so it never finishes configuration? Has anybody tried to simulate PCIe and created their own function calls in the BFM driver?

[Altera_Forum]

I used the Altera PCIe BFM along with there function calls, slow but works fine

[Altera_Forum]

At first, you can try use the static design examples for simulation that are available in Quartus installation directory. 

<install_dir>/ip/altera/altera_pcie/altera_pcie_a10_ed/example_design/a10  The driver is altpcietb_bfm_rp_gen3_x8.sv try the ebfm_barwr_imm procedure which writes up to four bytes of data to an offset from the specified Endpoint BAR. ebfm_barwr_imm(bar_table, bar_num, pcie_offset, imm_data, byte_len, tclass)  The ebfm_barrd_wait procedure reads a block of data from the offset of the specified Endpoint BAR and stores it in BFM shared memory. ebfm_barrd_wait(bar_table, bar_num, pcie_offset, lcladdr, byte_len, tclass)

[Altera_Forum]

--- Quote Start ---  At first, you can try use the static design examples for simulation that are available in Quartus installation directory. <install_dir>/ip/altera/altera_pcie/altera_pcie_a10_ed/example_design/a10  The driver is altpcietb_bfm_rp_gen3_x8.sv try the ebfm_barwr_imm procedure which writes up to four bytes of data to an offset from the specified Endpoint BAR. ebfm_barwr_imm(bar_table, bar_num, pcie_offset, imm_data, byte_len, tclass)  The ebfm_barrd_wait procedure reads a block of data from the offset of the specified Endpoint BAR and stores it in BFM shared memory. ebfm_barrd_wait(bar_table, bar_num, pcie_offset, lcladdr, byte_len, tclass)  --- Quote End ---    As I mentioned, I'm not even getting to the point in the driver file where my own test code runs. I'm stuck in configuration at state L0. Strangely, I get to L0, then it goes through the recovery sub-state machine, and then back to L0, where I'm stuck. I found this, but editing the .qsys file didn't help:  https://www.altera.com/support/support-resources/knowledge-base/ip/2017/what-assignments-do-i-need-for-a-pcie-gen1--gen2-or-gen3-design-.html

[Altera_Forum]

--- Quote Start ---  As I mentioned, I'm not even getting to the point in the driver file where my own test code runs. I'm stuck in configuration at state L0. Strangely, I get to L0, then it goes through the recovery sub-state machine, and then back to L0, where I'm stuck. I found this, but editing the .qsys file didn't help:  https://www.altera.com/support/support-resources/knowledge-base/ip/2017/what-assignments-do-i-need-for-a-pcie-gen1--gen2-or-gen3-design-.html  --- Quote End ---   The knowledge-base link mentioned above is only applicable for hardware test. But your case seems like is simulation.

[Altera_Forum]

--- Quote Start ---  The knowledge-base link mentioned above is only applicable for hardware test. But your case seems like is simulation.  --- Quote End ---    Yeah, I realized that after I tried it. I needed to make the changes anyway since eventually this will end up in hardware.