FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6343 Discussions

Hard memory controller IP for Cyclone V

Altera_Forum
Honored Contributor II
1,459 Views

Hello, 

 

Could you please point to how to access Hard memory controller (external DDR3) in Cyclone V from FPGA custom logic? Which is the IP core that allows to create generate IP core instance, place a symbol on the schematics and connect my logic? Is that IP free for evaluation or licensed? I am using Lite edition of Quartus.
0 Kudos
6 Replies
Altera_Forum
Honored Contributor II
439 Views

Hi,  

 

DDR3 SDRAM Controller with UniPHY is what you need. It uses Avalon MM interface for user acces. I have used it with Lite edition.
0 Kudos
Altera_Forum
Honored Contributor II
439 Views

Thank you for response. But how then I know that this DDR3 interface is not for soft memory controller generation? Do you mean that UniPHY denotes, that it is hard memory controller? Which IP is then for soft memory controller (also in case of DDR2).

0 Kudos
Altera_Forum
Honored Contributor II
439 Views

In DDR3 SDRAM Controller with UniPHY IP wizard there is an option to choose which to implement hard or soft controller. I don't have any experience with DDR2 in Cyclone V family but I think there is same otpion as in DDR3.

0 Kudos
Altera_Forum
Honored Contributor II
439 Views

 

--- Quote Start ---  

I don't have any experience with DDR2 in Cyclone V family but I think there is same option as in DDR3. 

--- Quote End ---  

 

It actually is. 

 

In case of DDR3 consider that Cyclone V doesn't support write leveling, means the memory layout must follow DDR2 signal layout rules and you can't use DDR3 memory modules (which makes limited sense anyway because the hard memory controller is limited to 32 bit data width).
0 Kudos
Altera_Forum
Honored Contributor II
439 Views

 

--- Quote Start ---  

It actually is. 

 

In case of DDR3 consider that Cyclone V doesn't support write leveling, means the memory layout must follow DDR2 signal layout rules and you can't use DDR3 memory modules (which makes limited sense anyway because the hard memory controller is limited to 32 bit data width). 

--- Quote End ---  

 

 

 

I was considering the following integration board https://www.opalkelly.com/products/zem5305/ . The specification tells that DDR3 is connected to Cyclone V. Are you saying that despite they write DDR3 I should use DDR2 hard memory controller?
0 Kudos
Altera_Forum
Honored Contributor II
439 Views

 

--- Quote Start ---  

Are you saying that despite they write DDR3 I should use DDR2 hard memory controller? 

--- Quote End ---  

 

No, use DDR3 controller.  

 

As I understand you are not planning to use memory modules (board of your provided link uses only one memory chip) so there is no need for write levelling anyway.  

 

Regards,  

Geros dienos :)
0 Kudos
Reply