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Hardware -> Nios II big data transfer

Altera_Forum
Honored Contributor II
980 Views

Hello, 

 

I'm having questions about how to send a big data buffer from my VHDL Hardware component to my Nios II. 

 

The problem with this buffer is that its size can vary from 90bits to 2000bits. 

 

What do you think is the best way to transfer these data from my hardware to my Nios II? 

 

With regards, 

Michel
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4 Replies
Altera_Forum
Honored Contributor II
77 Views

You need to write into memory the Nios can read, obvious options: 

1) Add an Avalon master interface to your vhdl component and write directly to any Avalon slave. 

2) Add an Avalon slave interface and use DMA (or direct access from the nios cpu). 

3) Dual port an internal memory block between your vhdl and the nios cpu.
Altera_Forum
Honored Contributor II
77 Views

Thank you for your answer dsl. 

Could you please explain what do you mean by dual port an internal memory block between my vhdl and my nios cpu? 

 

Can I do that with an onchip memory for instance? 

 

Thank you.
Altera_Forum
Honored Contributor II
77 Views

I think all the on-chip memories have 2 ports - so can be accessed by two vhdl components at the same time (with some contraints they can be in different clock domains as well). 

 

Thinks/remembers more... The SOPC builder will only expose the second interface as an Avalon slave (not the raw memory signals). So you either have to write the Avalon master interface (most of which probably doesn't get synthesised for the single-master -> single slave case), or write the Avalon slave -> internal memory login - there are probably lots of copies of that lurking - and put the memory inside your vhdl. 

 

Neither will allow you to use the faster 'tightly coupled data' interface on the cpu.
Altera_Forum
Honored Contributor II
77 Views

I see that I won't be able to use the tightly coupled data anyway so, what about writting a FIFO -> Avalon Streaming interface -> SGDMA -> Dual port Onchip memory (S1 on the SGMDA, S2 on the Nios II Data master) -> Nios II (IOWR/IORD direct access) ? 

 

Or should I rather just write an Avalon master interface -> Dual port Onchip memory (S1 on the Avalon Master, S2 on the Nios II Data master) ? (which would be easier I guess) 

 

Thank you again dsl.
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