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I am working on interfacing Stratix 4 GX FPGA with DDR2. I used uniphy ip core in Megawizardpulgin tool. I got full files and i simulated example design with provided testbench (in modelsim). its working properly. But when I tried to simulate my top level vhdl code alone, some errors are comming.
"# Fatal error in Process MEMORY at C:/altera/12.1/modelsim_ase/win32aloem/../altera/vhdl/src/altera_mf/altera_mf.vhd line 39940".
how to proceed?
can you suggest a proper way to simulate my top level vhdl code?
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What steps that you had use to simulate your DDR2?
Here is the steps for simulation DDR2 https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_debug.pdf
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Hello,
Currently we are doing a project which focus on SFPDP, DDR2, SATA
Tool: Quartus II(14.0), Modelsim (vhdl)
FPGA: Stratix 4 GX
We are planning to use ALTGX, ALTGX_RECONFIG, UNIPHY etc. mega functions for the development of the system. We would like to have proper guidance for doing this.
Can you provide 1-2 weeks hands on training on above mentioned IP cores? or the procedure for doing so.
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HI,
Thanks for your interest in using FPGA products but I also would like to share with you Stratix IV FPGA is a legacy product while Quartus v14.0 is too old, obsolete version.
My advice to you as below
- Sorry but I foresee it's unlikely to get any hands on training for legacy FPGA product. I propose to migrate to newer generation of FPGA product if possible like the 10th series FPGA family - Cyclone 10 GX for instance to get better technical support
- Yet, if you still prefer Stratix IV FPGA then feel free to checkout below online training course (some are free, some are paid service)
- https://www.intel.com/content/www/us/en/programmable/support/training/legacy.html
- Or you can also google for the IP user guide doc as well
- Another thing to take note is to upgrade to latest Quartus version if possible (v19.1 standard edition) as v14.0 is already obsolete.
Thanks.
Regards,
dlim

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