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Altera_Forum
Honored Contributor I
730 Views

Help,Problem with DDR2 HPCII simulation

I have a design using DDR2 HPCII controller(with Altmemphy) in Cylone IV.When I simulate the this HPCII controller with Micron 1Gb DDR2 simulation model,strange things happened:1)when simulating the example design,block read and block write is ok.2)when simulating only block write with my design ,simulation is ok.3)when simulating only block read with my design,simulation is ok.4)when simulting first block write(1024DW) and when block read(1024DW) with my design,write is ok,but nothing can be read out. In the error situation, I find all read requests have been sent to DDR2 HPCII controller,but HPCII didn't send request signals on AFI interfaces. Can anybody tell me why? Are there some contraints in using DDR2 HPCII controller?? By the way,local_init_done signals is high already.

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Altera_Forum
Honored Contributor I
20 Views

Problem solved!