I need help/pointers for debug of Backplane Auto Negotiation.
- Arria10 FPGA <=> Copper Backplane <=> AMD SoC
- Both partners are capable of 10G and 1G modes
- I have matched the Pause ability on both side -- i.e. only enabled C0
- FPGA does not believe it's getting valid DME packets. SignalTap shows :
- an_rx_idle goes high and stay HIGH indefinitely
- an_pg_received is stuck at LOW
- the dme_in bus is showing a constant value of 10100009C0100009C (hex)
Any pointers on how to debug will be very helpful. Thank You in advance!
Yes, I am using the 1G/10G Ethernet IP in Arria10.
- FPGA believes to be sending the right DME -- I can see it in SignalTap
- But, I don't see the AMD registering that information -- I see this by reading the LP registers using the MDIO interface
- The same happens in reverse direction:
- i.e. AMD believes it is sending information (again, I read the advertised/tech registers using MDIO interface) ...
- but, FPGA is not registering these values in the LP registers ... actually, I don't even see the page_received signal go high.
Please share any tips/tricks/information you may have with Arria10 experience. Thank You very much in advance!
Hi Chee Pin,
In the XCVR PHY User Guide: 2.6.3. 10GBASE-KR PHY IP Core This is the IP I am using for 10g Backplane interface (1-lane).
Those signals are inside the IP -- not the signals/interfaces available at top level to a user
If you go down to the level where Sequencer is instantiated, you will see those signals.
Hi Chee Pin, Answer to your questions:
I cannot perform the loopback on the copper backplane. I tried internal serial loopback. The Link stays in AN mode (does not exit). For some reason, the rx_parallel_data_navtive[63:0] is stuck at 0100009C0100009C0h
I have not yet done Simulation. I will try that in next couple of days.
At top level I see: pcs_mode[5:0] = 00001 | all LED signals are LOW | rx_data_ready=0 | rx_block_lock=0 | rx_hi_ber=0
I will attach the IP .qsys file with this update. Please rename the file to .qsys (I had to change extension because this website wont allow me to upload the file as-is).
I did a experiment: I forced 10G mode on the FPGA and AMD SoC. I am able to pass 10g traffic when both are forced to 10g mode. This tell me that the two PHYs and the physical connection are doing what they are supposed to do.
Please let me know what you think. Thank You in advance!