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Honored Contributor I
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Help with DDR2 SDRAM DIMM with UniPHY on Stratix III eval board

Hi, 

 

I am trying to use the DDR2 SDRAM DIMM on the Stratix III eval board. 

http://www.altera.com/products/devkits/altera/kit-siii-host.html 

 

I am following the directions at: 

http://www.alterawiki.com/wiki/design_example_-_stratix_iii_ddr2_sdram_uniphy_400mhz_x72 

 

The design seems to synthesize fine. After boot, calibration succeeds, so I think some parts of the DDR2 system are working. But when I try to trigger a single read on Avalon, I never get a response. 

I'm following the signals described on p 3-9 of http://www.altera.com/literature/manual/mnl_avalon_spec.pdf 

 

This is using Quartus 13.1. 

 

Any suggestions on how to troubleshoot this? Thanks. 

 

Also, since I'm using a stock eval board with the stock SDRAM DIMM, perhaps there is a reference implementation somewhere? 

 

Thanks very much, 

J.
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