FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5881 Discussions

High Speed Intel Reed Solomon FPGA IP Core Documentation does not provide details, see questions in section Details.

ACHAD
Beginner
835 Views

1. The field polynomial in the decoder section does not have any information on how it should be used. I am using it for Infiniband and believe it is the same as Ethernet. On what basis should I select one of the many choices in the drop down menu in Platform Designer.

2. When turning on Decoding Failure and Error Symbol Count, there is no way to tell which bits correspond to the Decoding Failure and which ones to the Error Symbol Count. All I see is 4 extra bits on the output of the decoder i.e. data bits out = data bits in +4.

3. The latency selection in Platform Designer changes from say 93 to 45 (same for some other selections). What is the correct number?

0 Kudos
1 Reply
Vicky1
Employee
89 Views

Hi,

First you need to become familiar with working of Reed-Solomon Codes. Refer the "Reed-Solomon Codes" from below link

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/g709_wp.pdf

Refer "Figure 3–1. RS Codeword Example" from below link

https://www.intel.co.jp/content/dam/altera-www/global/ja_JP/pdfs/literature/ug/rs-compiler_ug.pdf

For Latency selection check " Performance and Resource Utilization" for given devices from the link below that might helps to you.

https://www.intel.cn/content/www/cn/zh/programmable/documentation/dmi1424790284305/dmi1424790559225....

 

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

 

 

 

 

Reply