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HBhat2
New Contributor I
323 Views

High-Speed Reed-Solomon IP Core

Hi,

 

I need to know the descriptions of following signals i the RS FEC decoder module. I didn't get much info in the IP user guide (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_rsii_hs.pdf).

1) out_decfail - When this signal will be set. How to reset this failure?

2)out_errors_out- This include the corrected errors or even uncorrected errors if more bit errors in the received data

3)out_errorvalues_out- What is the value of this set of signals? 

 

With regards,

HPB

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6 Replies
CheePin_C_Intel
Employee
62 Views

Hi,

 

As I understand it, you have some inquiries related to some of the HS RS output ports. As I look into the user guide, it seems like there is not much details as you mention. Please allow me some time to further consult Factory for further insight.

 

Thank you.

CheePin_C_Intel
Employee
62 Views

Hi,

 

As per my discussion with peers, the following are our understanding for your reference:

 

1) out_decfail - When this signal will be set. How to reset this failure?

[CP] This signal will be asserted when the errors within a packet exceed the decoder's correction capability. This signal should assert together with EOP and de-assert for a new packet.

 

2)out_errors_out- This include the corrected errors or even uncorrected errors if more bit errors in the received data

[CP] This shows the number of corrected errors. When the out_decfail is asserted, this output may be no longer valid. 

 

3)out_errorvalues_out- What is the value of this set of signals? 

[CP] This bus shows the raw symbol with error. The corrected symbol or decoded symbol will be at out_symbols_out.

 

It is recommended for you to perform a Modelsim simulation to further verify the IP behavior based on your target implementation.

 

Please let me know if there is any concern. Thank you.

 

 

Best regards,

Chee Pin

HBhat2
New Contributor I
62 Views

Hi @cheepinc_Intel​ ,

 

Thank you for detailed description. I was looking for the similar description in the user guide.

Yes, I am running the simulation using Modelsim. I enabled the above set of options in the decoder. As I am initially working with Encoder to decoder loopback, I was inserting some errors and checking. But, unable to understand the meaning of above status bits. Now I will decode these status bits as per description provided by you.

 

With regards,

HPB

CheePin_C_Intel
Employee
62 Views

Hi, Thanks for your update. Sorry for the confusion with the user guide. Please feel free to share with me your finding if you observe any anomaly with my description vs your simulation. Thank you. Best regards, Chee Pin
HBhat2
New Contributor I
62 Views

Hi @cheepinc_Intel​ ,

 

There is one more option called "Hyper-Optimization". What role does this option play for the RS FEC Decoder IP? Even, there is no description for "Hyper-Optimization" field in the user guide. How the low, medium, high settings effect the functionality ?

 

With Regards,

HPB

CheePin_C_Intel
Employee
62 Views

Hi HPB,

 

Sorry for the delay. I might have overlooked the email notification of your latest inquiry on the Hyper-Optimization. Yes, you are right, there seems to be no specific explanation on this parameter in the user guide. Sorry for the inconvenience.

 

For your information, the Hyper-Optimization parameter is for the S10 Hyper register optimization usage. The following is the description from the Q18.1Pro S10 HSRS IP parameter editor -> Details for your reference:

 

"Insertion of register stages to optimise for Stratix 10 and later architecture"

 

Please let me know if there is any concern. Thank you.

 

 

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