I am using High-Speed Reed-Solomon Intel FPGA IP for (198,194 ) block size and polynomial of 285h. In simulation I see that there is a latency of 10 cycles from first input data valid to first valid output data from the Encoder. Is there any way to reduce this latency?
I have attached the Encoder setting snapshot as well as simulation snapshot for the reference.
As I understand it, you would like to inquire if there is a way to reduce the encoder latency for your specific configuration. For your information, as I look through the user guide, it seems like there is no specific option for user to configure the latency for the encoder. If I understand it correctly, the latency would be dependent on your specific configuration. Sorry for the inconvenience.
Please let me know if there is any concern. Thank you.