FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6462 Discussions

High Speed Reed-Solomon Modelsim simulation

HBhat2
New Contributor II
947 Views

Hi,

 

I created a Simple project with High Speed RS-FEC encoder and decoder and generated the Test bench systems. After generating the files, I opened Modelsim (both quartus and Modelsim version is 18.1) and ran "source msim_setup.tcl"

I observed that none of the files got compiled and work library shows empty. I captured the log and attached for the reference. Please suggest me how to proceed with the simulation.

 

With Regards,

HPB

0 Kudos
3 Replies
CheePin_C_Intel
Employee
579 Views
Hi HPB, As I understand it, you seems to have some inquiries related to the Modelsim simulation with the HSRS IPs. Just would like to check with you, after you ran "source msim_setup.tcl", did you have had a chance to type "ld" command in the Modelsim to start the library compilation and elaboration? Please let me know if after running "ld", there is still no compilation running. Thank you.
0 Kudos
HBhat2
New Contributor II
579 Views

Hi @cheepinc_Intel​ ,

 

You are right. It is my mistake. After Ld command, the simulation is launched. Thank you for your support.

 

With regards,

HPB

0 Kudos
CheePin_C_Intel
Employee
579 Views
Hi HPB, Thanks for the update. Glad to hear that you are able to run the simulation now. Thank you.
0 Kudos
Reply