I am trying to follow the example in the Intel® Arria® 10 and Intel® Cyclone®
10 GX Avalon®-MM Interface for PCI Express* User Guide 6.8.3 “Examples of Reading and Writing BAR0 Using the CRA Interface”
I am able to read just fine, but the writes do not seem to work.
After the write, I never get a completion packet (0x2010 bit 0 never goes high). Are there other registers that need to be configured first for this to work? I am not using a CPU in this design and I need to configure the root port from FPGA logic.
After following the link you provided to the FPGA Design Tools Forum, "FPGA Design Tools" is not one of the options in the "Post To" drop down box when posting questions.
FPGA Intellectual Property was the closest category I found.
Please elaborate on where you would like me to post this question about the PCI Express IP core.