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I am trying to access data from a DDR4 SDRAM connected to an Arria 10 and store it in a fifo buffer sequentially, and I read that you can use an emif hard memory controller to access the DDR4 memory through the avalong mm interface, but I do not know how I would go about doing it . I am quite new to using FPGAs so any help would be much appreciated.
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Hi,
You can refer to this Avalon handbook which defines all the Avalon interfaces and how it operate in details --> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf
Hope this helps.
Regards,
NAli1
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