How does Qsys compute BAR sizes for Avalon-MM PCIe?

[corestar]

I'm attempting to use the "Avalon-MM Cyclone V Hard IP for PCI Express" core. I created an example design modeled after:

C:\intelFPGA_lite\19.1\ip\altera\altera_pcie\altera_pcie_cv_hip_avmm\example_designs\ep_g1x1.qsys

It has the following BAR but I can't figure out where it gets the sizes.

The user guide says:

What parameters? There is nothing else in the ep_g1x1.qsys that matches those sizes? 

And in my own attempt (see attached), it says:

The root complex sees the FPGA, but sees 0 sizes for the BAR's.

[corestar]

Partially figured it out myself. It's apparently not allowed to export the Rxm_BARX and Txs buses. It's clumsy, but I created Avalon to External Bus Bridge to connect to the Rx buses and an "External Bus to Avalon Bridge" for the Tx bus. The BAR sizes match the address sized in the bridge.

Still does not explain the example ep_g1x1.qsys where BAR0 is connected to a 4 KB block RAM and yest has a size of 4 MB.

[FvM · Accepted solution]

Hi,
BAR sizes are defined by the address map. Review chapter "Minimizing BAR Sizes and the PCIe Address Space" in Cyclone V AVMM for PCIe user manual.

[corestar]

Ok, I see. For my example, it automatically computed the address map based on the slaves attached to the BARs.

In the ep_g1x1.qsys example, they must have manually entered them:

The nearest power of 2 greater than 0x201000 is 22 to get the 4 MB for BAR0. Same for BAR2 with 2^15 being lowest power of 2 greater than 0x402F.

Thanks

[Wincent_Altera]

Hi,

Thanks FvM for helping on that, So do you still have any further question on this forum ?

Regards,
Wincent_Intel

[Wincent_Altera]

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[corestar]

@Wincent_Altera 

Sorry, I see you asked if I have any further questions. Not at the moment. @FvM answered the main question. I've decided not to use the Avalon-MM PCIe and am using the Avalon-ST interface instead.

Thanks,