How does altlvds make bit alignment?

[Altera_Forum]

Hi, 

 I'm currently using Cyclone III and trying to deserialize an LVDS data.  It has 5 channel and 7bit data. 75MHz clock, deserialize factor is 7.  I would like to ask a question.  I want to see RGB bits one by one at the parallel output of altlvds_rx block.  Which pins are RGB bits? How can I know? There are 35 bits at the output of altlvds_rx block.  There is no problem on the screen of LCD-TV.Succeded to serialize-deserialize.  I could find hsync,vsync and DE(data enable) bit.  Please help me.

[Altera_Forum]

How come you only have one post and already have a Rep Power of 238 ?

[Altera_Forum]

The thread is already 1 year old but i'm interested 

in new insights how the ALTLVDS_RX alligns the bits.  did you figure that out?

[Altera_Forum]

You need to use the altlvds_rx IP core with an external frame clock with a frequency determined by the data bit-rate and LVDS deserialization factor. The bits are then packed into parallel words with respect to the frame clock. 

 For an example, see this document, p71:  http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/digitizer_tests.pdf)  Cheers, Dave

[Altera_Forum]

In my case I have 4 LVDS data channels (A0-A3) and the dedicated CLK channel. 

Each of these data channels has 7 bits therfore 28bits. (8xR, 8xG, 8xB + 1x hsync, 1x vsync, 1x DataEnable (DE) and 1x NA)  I configured my ALTLVDS_RX with 4 channels and 7 for the deserialization factor. Consequential i have 28 output signals RX_OUT[27..0].  The problem is that I don't know which of these signals belongs to which output signals.  Is there a documentation how the deserializer assigns the bits to the output signals?  http://i41.tinypic.com/33le2vt.jpg

[Altera_Forum]

When in doubt, simulate. Modelsim will be able to answer your questions. 

 Put in a serial bit stream at the data rate you want to deserialize, or instantiate an altlvds_tx to generate the serial data.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  In my case I have 4 LVDS data channels (A0-A3) and the dedicated CLK channel. Each of these data channels has 7 bits therfore 28bits. (8xR, 8xG, 8xB + 1x hsync, 1x vsync, 1x DataEnable (DE) and 1x NA)   I configured my ALTLVDS_RX with 4 channels and 7 for the deserialization factor. Consequential i have 28 output signals RX_OUT[27..0].   The problem is that I don't know which of these signals belongs to which output signals.   Is there a documentation how the deserializer assigns the bits to the output signals?  --- Quote End ---     Search for 'rx_channel_data_align' in the LVDS SERDES Transmitter/Receiver (ALTLVDS_TX and ALTLVDS_RX) Megafunction User Guide. In particular, take a look at the following: - Page 2-13 (page 15) which describes how you manually align the bits - Page 3-8 (page 36) which describes this process in more detail.   I was a bit surprised when first encountering this years ago, having become used to commercial Camera Link parts which lock on and define bits relative to the input clock (not the higher speed bit clock).   Kevin Jennings