FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5881 Discussions

How interfacing HPC.II "local_signals" (ddr controller) with vhdl logic ?

Altera_Forum
Honored Contributor II
716 Views

Hi, 

 

I would like to use the ddr/ddr2 IP HPCII with altmemphy without nios : 

- HPC 2 full rate, quartus 10.1sp1 

- DDR 32MB x16, burst length = 4 (=> local_size=2) 

 

My problem is that HPC interfacing (local_xxx signals) documentation is very poor. The purpose of every signal is explained (page 454/458) but not how to manage write/read burst operations with these signals. There is only two diagrams (page 494/498) with a very few explanations. 

http://www.altera.com/literature/hb/external-memory/emi_archive_101.pdf 

 

I don't know very well ddr devices, so I need more information. Especially I don't understand : 

- rows have to be open before write commands with a fake request ? 

- write diagram (page 496): why burst_begin is toggling (what about data when burst_begin=0??) and address is incremented only every 2 clk cycle (not when burst_begin=0) ? 

- do local_xxx signals respect specific timings ? 

- local_data width is 32b => addresses increment is 2 ? 

... 

 

Thanks for your help, 

 

Sebastien
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
69 Views

Same questions here. I managed to make it work by doing exactly what's in the official timing diagrams [1], but I don't understand what's going on completely. 

 

I'm pretty sure that the local_xxxs form an Avalon MM interface, the problem is the literature is scarce and misleading [1], [2]. 

 

[1] http://www.altera.com/literature/hb/external-memory/emi_altmemphy_ref_timing_diagram.pdf 

[2] http://alterawiki.com/wiki/interfacing_to_altera_external_memory_controller_ip 

 

Thanks, 

Leo
Reply