1) There are some TimeQuest warnings regarding output paths not or not full constrained (All LVDSp/n and LVDS-Clkp/n paths)
2) Please take a look in the thread
"MAX10 using external PLL with soft-lvds gives always a warning:
Warning (15064): PLL... jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance"
for more details answered from JwChin
I am pretty sure it is because you are not using dedicated PLL output pins. What device are you and which one of the PLLs are you using?
I am also looking for help on how to SDC constraints for soft LVDS RX and TX, but find very little on that subject. None of the example project with soft LVDS has any SDC constraints on it!
Yes, the jitter warning depends on using non dedicated pins. The TimeQuest warnings go away if I use "max-skew" sdc cmds for all LVDS ports. Although the timing variation (max-skew) for all outputs are fixed the cmd is nessessary for TimeQuest.