I have a relatively large combinational block that is mapped to an Intel FPGA using Quartus Prime Pro.
I recently learned that an ALM can provide the output either directly from an adaptive LUT or from a register that latches the value of the LUT.
I was wondering if it is possible to automatically convert the blocks from combinational to sequential, which results in a deeply pipelined design.
In my view, one need to rewrite the RTL for sequential implementation. It is not possible to map combinational logic to sequential with the help of tool.
The Quartus tool maps the logics based on RTL code either to LUT or registers.