I think I am not editing my custom component in the correct way. I have been doing the following to debug my component.1) Edit VHDL file in /syntesis/submodules and save it. 2) Generate .sof file with Quartus and upload it to the board. 3) Run my C code. Sometimes I see that my VHDL file in /syntesis/submodule becomes empty. Sometimes I see that a the changes I do in VHDL file doesn't make any change in component behavior. The creation of the component is not a problem: I added .qip to my project. Please let me know how do I edit the VHDL file of my custom component!
The Qsys environment will generated code into the synthesis/submodule folder. When it does this it will overwrite all the files in that folder. So if u make a change in a file in the submodule folder and the regenerate Qsys for some other reason your changes will be lost. You should edit the original files for the component of interest that Qsys is reading to generate your design. Then the changes will be carried over into your submodule folder
Ok. If I understand well, it means that if I don't regenerate my Qsys system, I can edit the file the way I am doing. correct?Thank you, Krasner. Gustavo
That is correct. Quartus can be a little weird, so when you edit the file and save it, make sure you click out of the file (say to another quartus tab) and click back in to check if the changes really did get saved. Basically, you always want to make sure you are compiling the latest files.