The Stratix V DSP block supports many modes. The mode I'm interested in is two independent 18x18-bit input with 32-bit output (as described in the device handbook section 3-2 "Supported Operational Modes in Stratix V Devices").
I've tried (in Quartus 15.1):
1) Inference:
reg A, X;
reg B, Y;
reg C, Z;
always @(posedge Clk) begin
C <= A * B;
Z <= X * Y;
end
2) LPM_MULT megafunction
3) ALTERA_MULT_ADD megafunction
None of those work. They all use 2 DSP blocks for two multipliers. I need to use two multipliers per DSP block in order to make the design fit into the device.
Any assistance in forcing the compiler to use the intended mode would be greatly appreciated.
