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How to generate ALLPLL in S10 ?

minjoolee
Employee
380 Views

Hi, 

 

I am tried to converter old pll in quartus 13.1 to quartus pro 21.x

 

OLD ALLPLT has scanclk/scandataout port from tool .

 

 

minjoolee_0-1641905691773.png

 

// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_cnfgrbl (
areset,
configupdate,
inclk0,
scanclk,
scanclkena,
scandata,
c0,
c1,
c2,
locked,
scandataout,
scandone);

input arese

 

 

 

how to generate same PLL for s10 ?

I can't see scanclk/scankena/scnadata pin option in quartus pro 21.x

 

 

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3 Replies
sstrell
Honored Contributor III
369 Views

That IP is not compatible with S10.  You have to create a new Intel PLL IP for it and copy over the settings.  The options you mention may not be available for the newer PLL.

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minjoolee
Employee
364 Views

I know that I have to generate,

 

but how to do  for ALLPLL.

 

in IOLL itel FPGA IP from quatur pro, 

 

doesn't have

 

scanclk,
scanclkena,
scandata,

 

these pins. 

That is why I don't re-generation. 

 

 

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Ash_R_Intel
Employee
359 Views

In ALTPLL the scanclk, scandata etc are used for Dynamic Reconfiguration. In S10, PLL is different and the reconfiguration functionality can be achieved using IOPLL Reconfig Intel® FPGA IP Core: https://www.intel.com/content/www/us/en/docs/programmable/683195/20-3/core-references-14991.html


Also, the Dynamic phase shift ports are different: https://www.intel.com/content/www/us/en/docs/programmable/683195/20-3/dynamic-phase-shift-ports-in-the-ip-core.html


Regards


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