How to implement PCIE hard IP for Cyclone IV GX

[PiotrWo]

Hi,
I am currently working with a Cyclone IV GX FPGA: EP4CGX75CF23C7. I would like to run a PCI transceiver and map the memory (on-chip memory) to the endpoint using 1 data lane. What do I need for this in quartus II 23.1 or 24.1? I see IP_Compiler for PCI Express but I cannot find any compatible instructions on how to use it.
Thanks.

[FvM]

Hi,
what do you mean "I cannot find any compatible instructions on how to use it." There's a user guide: https://cdrdv2-public.intel.com/655049/ug_pci_express.pdf

[PiotrWo]

Hi,

Thanks for your help. I need some time to review the document, I hope it will help me solve the problem.

All the best

P.

[Wincent_Altera]

Hi FVM,

Thanks for your help in the community question.

Hi PiotrWo,

I believe your queries about unable to find instruction to use IP compiler had been address by our community expert.

Is there anything else you think we could help you ?

Regards,

Wincent_Altera

[Wincent_Altera]

Hi PiotrWo,

If you have further question, please file a new thread.
Altera and the FPGA community will be full commitment to support you.

Regards,

Wincent_Altera