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DHUAN26
Beginner
1,223 Views

How to initialize the Configuration Space when PCIe core in Root port mode?

I can read Device id and Vendor id of Root Port, but can not read Device id and Vendor id of Endpoint by user logic.

PCIe core connect with only one Endpoint,and only one lane.

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5 Replies
Nathan_R_Intel
Employee
106 Views

Hie,

 

Device ID and Vendor ID is just a HDL parameter. It can be changed in the PCIe Phy IP. Even if you have not changed the Device ID and Vendor ID; Intel-PSG has default values like 0x00001172 for vendor ID. Hence, not able to read this numbers should not be attributed by FPGA configuration or design. 

However, if your PCIe does not link up, then its possible the configuration registers are not updated; which will not enable the endpoint to be detected.

Please check if you PCie one lane has link up successfully.

 

Regards,

Nathan

 

 

DHUAN26
Beginner
106 Views

I can read out 0x00001172 of my Root Port Hard IP and ltssmstate == 5'h0F ( L0 state ).

TLP on alalon is CfgRd0({fmt,tppe} = 8'h04),64'h0000000F04000001 + 64'h0000000000000000

and read out value is 32'h0a101172.

 

However,

TLP on alalon is CfgRd1({fmt,tppe} = 8'h05),64'h0000000F05000001 + 64'h0000000000000000

I can not see TLP reply from End Point,which is a PMC chip.

DHUAN26
Beginner
106 Views

"Sets the Root Port Configuration Space to enable the Root Port to send transactions on the PCI Express link." in ug_a10_pcie_avst 17.8.3 section.

How to enable detail?

If set command register to 16'h0007 by TLP on alalon is CfgWr0({fmt,tppe} = 8'h44),64'h0000000F44000004 + 64'h0000000000000007,can I enable it?

Nathan_R_Intel
Employee
106 Views

Hie,

 

There could be various reasons why you cannot get a TLP reply from a EP. Hence, you will need to debug further. I believe you are currently following our user guide recommendation that before you issue transactions to the Endpoint, you must configure the Root Port and Endpoint Configuration Space registers. 

 

I am sorry, it is diffcult to understand what your trying to enable using the CfgWr0. Hence, I don't have enough information to advice on this. As for using the Config Type 0 write Request, you could refer to our user guide on the rules.

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf

 

Regards,

Nathan

RWitt
Beginner
106 Views

DHUAN26 - did you get any further? By the way - in one of your examples above remember that the register is shifted two bits in the config header, just a warning.

 

I'm trying to write the 0x18 register of the Arria-10 RootPort, with a value 00010100 - so the downstream bus would be 1, subordinate bus 1 (only one bus downstream). The write occurs to the RP on the Avalon bus, the RP responds with a status = success, but when I read that register I always get back 00s. Like DHUAN - I can read the dev-id (info configured in Platform Designer), I just can't write anything through the ST interface.

Anyone have success doing that?

I'm guessing I could move the config-space registers external, or use the LMI, but before that - this TLP method on the ST interface is supposed to work.

Regards,

Bob

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