How to messure the Delay of CPRI IP, T_R1

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

How to messure the Delay of CPRI IP, T_R1

1,062 Views

In the Ug_CPRI,page 4-33, For CPRI RX PATH, There are The data delay to and through the CPRI MAP receiver block consists of the following measurable delays:

Delay to synchronization pulses cpri_rx_rfp and cpri_rx_hfp

Delay to assertion of the signal cpri_rx_start

Delay to deassertion of the following pulse on the signal mapN_rx_resync

I wonder know how to measure these delay value?

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.